JPH0333068Y2 - - Google Patents

Info

Publication number
JPH0333068Y2
JPH0333068Y2 JP1985146750U JP14675085U JPH0333068Y2 JP H0333068 Y2 JPH0333068 Y2 JP H0333068Y2 JP 1985146750 U JP1985146750 U JP 1985146750U JP 14675085 U JP14675085 U JP 14675085U JP H0333068 Y2 JPH0333068 Y2 JP H0333068Y2
Authority
JP
Japan
Prior art keywords
heat dissipation
resin
stud
packages
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1985146750U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6255354U (en]
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985146750U priority Critical patent/JPH0333068Y2/ja
Publication of JPS6255354U publication Critical patent/JPS6255354U/ja
Application granted granted Critical
Publication of JPH0333068Y2 publication Critical patent/JPH0333068Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
JP1985146750U 1985-09-26 1985-09-26 Expired JPH0333068Y2 (en])

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985146750U JPH0333068Y2 (en]) 1985-09-26 1985-09-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985146750U JPH0333068Y2 (en]) 1985-09-26 1985-09-26

Publications (2)

Publication Number Publication Date
JPS6255354U JPS6255354U (en]) 1987-04-06
JPH0333068Y2 true JPH0333068Y2 (en]) 1991-07-12

Family

ID=31059500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985146750U Expired JPH0333068Y2 (en]) 1985-09-26 1985-09-26

Country Status (1)

Country Link
JP (1) JPH0333068Y2 (en])

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7772036B2 (en) * 2006-04-06 2010-08-10 Freescale Semiconductor, Inc. Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing

Also Published As

Publication number Publication date
JPS6255354U (en]) 1987-04-06

Similar Documents

Publication Publication Date Title
US6198163B1 (en) Thin leadframe-type semiconductor package having heat sink with recess and exposed surface
US6790710B2 (en) Method of manufacturing an integrated circuit package
TWI453838B (zh) 具有散熱器之無引線封裝
US7489021B2 (en) Lead frame with included passive devices
JP2005191240A (ja) 半導体装置及びその製造方法
JPH11514149A (ja) 熱特性が改善された電子パッケージ
US5299091A (en) Packaged semiconductor device having heat dissipation/electrical connection bumps and method of manufacturing same
US6798046B1 (en) Semiconductor package including ring structure connected to leads with vertically downset inner ends
JP2000003988A (ja) リードフレームおよび半導体装置
US6661081B2 (en) Semiconductor device and its manufacturing method
KR100621555B1 (ko) 리드 프레임, 이를 이용한 반도체 칩 패키지 및 그의 제조방법
JPS60167454A (ja) 半導体装置
US20220157700A1 (en) Two sided bondable lead frame
JP2651427B2 (ja) 半導体装置の製造方法
JPH0333068Y2 (en])
JPH03174749A (ja) 半導体装置
JPH0228356A (ja) 表面実装型半導体装置及びその製造方法
JPH04155949A (ja) 樹脂封止型半導体装置
JPH05243326A (ja) 半導体装置
KR100252862B1 (ko) 반도체 패키지 및 그의 제조방법
JPH04196471A (ja) 半導体装置
JPH03237747A (ja) 半導体装置
JPS6244545Y2 (en])
JPH05251502A (ja) フィルムキャリア半導体装置
JPS62213145A (ja) 半導体装置用リ−ドフレ−ム